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1 typical application features description 60v low i q , triple output, buck/buck/boost synchronous controller the lt c ? 3899 is a high performance triple output (buck/ buck/boost) dc/dc switching regulator controller that drives all n-channel synchronous power mosfet stages. the constant frequency current mode architecture allows a phase-lockable frequency of up to 850khz. the ltc3899 operates from a wide 4.5v to 60v input supply range. when biased from the output of the boost converter or another auxiliary supply, the ltc3899 can operate from an input supply as low as 2.2v after start-up. the gate drive for the ltc3899 can be programmed from 5v to 10v to allow the use of logic-level or standard-level fets and to maximize efficiency. internal switches in the top gate drivers eliminate the need for external bootstrap diodes. the 29a no-load quiescent current extends op- erating run time in battery - powered systems . opti - loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. high efficiency wide input range dual 5v/8.5v converter efficiency vs output current applications n dual buck plus single boost synchronous controllers n wide bias input voltage range: 4.5v to 60v n outputs remain in regulation through cold crank down to a 2.2v input supply voltage n buck and boost output voltages up to 60v n adjustable gate drive level 5v to 10v ( opti-drive) n no external bootstrap diodes required n low operating i q : 29a (one channel on) n 100% duty cycle for boost synchronous mosfet n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n very low dropout operation: 99% duty cycle (bucks) n low shutdown i q : 3.6a n fixed or adjustable boost output voltage saves i q n small 38-lead 5mm 7mm qfn and tssop packages n automotive always-on and start-stop systems n distributed dc power systems n multioutput buck-boost applications l, lt , lt c , lt m , burst mode, opti-loop, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. 68.1k 649k tg1 run1, 2, 3 ltc3899 v bias 0.1f 0.1f 0.1f 4.9h 1.2h 3m 68.1k 357k v out1 5v 5a v out2 8.5v 3a 9m bg1 v fb1 v fb2 sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + drv cc intv cc drvset boost1 tg3 boost3 sw3 bg3 ith1,2,3 v fb3 sw1 tg2 bg2 gnd boost2 sw2 6.5h 15m 220f 33f 0.1f 4.7f 33f v out3 regulated at 10v when v in < 10v follows v in when v in > 10v v in 2.2v to 60v (start-up above 5v) 68f 3899 ta01a vprg3 output current(a) 0.01 efficiency (%) 95 94 92 90 93 91 89 88 1 3899 ta01b 10 0.1 v in = 12v v out = 5v burst mode operation 5v 6v 8v 10v gate drive (drv cc ) ltc 3899 3899fa for more information www.linear.com/ltc3899
2 absolute maximum ratings bias input supply voltage ( v bias ) .............. C0.3 v to 65 v topside driver voltages boost 1, boost 2, boost 3 .................. C0.3 v to 76 v switch voltage ( sw 1, sw 2, sw 3) ................ C5 v to 70 v drv cc , ( boost 1- sw 1), ( boost 2- sw 2), ( boost 3- sw 3) ........................................... C0.3 v to 11 v bg 1, bg 2, bg 3, tg 1, tg 2, tg 3 .......................... ( note 8) run 1, run 2, run 3 voltages ..................... C0.3 v to 65 v sense 1 + , sense 2 + , sense 1 C sense 2 C voltages ..................................... C0.3 v to 65 v sense 3 + , sense 3 C voltages ..................... C0.3 v to 65 v (notes 1, 3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 ith1 v fb1 sense1 + sense1 ? freq pllin/mode ss3 sense3 + sense3 ? v fb3 ith3 intv cc run1 run2 run3 sense2 ? sense2 + v fb2 ith2 vprg3 track/ss1 tg1 sw1 boost1 bg1 sw3 tg3 boost3 bg3 v bias extv cc drv cc bg2 boost2 sw2 tg2 track/ss2 drvset 39 gnd t jmax = 150c, ja = 25c/w exposed pad (pin 39) is gnd, must be soldered to pcb 13 14 15 16 top view 39 gnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1freq pllin/mode ss3 sense3 + sense3 ? v fb3 ith3 intv cc run1 run2 run3 sense2 ? sw1 boost1 bg1 sw3 tg3 boost3 bg3 v bias extv cc drv cc bg2 boost2 sense1 ? sense1 + v fb1 ith1 vprg3 track/ss1 tg1 sense2 + v fb2 ith2 drvset track/ss2 tg2 sw2 23 22 21 20 9 10 11 12 t jmax = 150c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb pin configuration pllin / mode , freq , drvset voltages ....... C0.3 v to 6 v extv cc voltage ......................................... C0.3 v to 14 v ith 1, ith 2, ith 3, v fb 1 , v fb 2 voltages ......... C0.3 v to 6 v v fb 3 voltage ............................................... C0.3 v to 65 v vprg 3, voltage ........................................... C0.3 v to 6 v track / ss 1, track / ss 2, ss 3 voltages ...... C0.3 v to 6 v operating junction temperature range ( note 2) ltc 3899 e , ltc 3899 i ......................... C40 c to 125 c ltc 3899 h .......................................... C40 c to 150 c ltc 3899 mp ....................................... C55 c to 150 c storage temperature range .................. C65 c to 150 c ltc 3899 3899fa for more information www.linear.com/ltc3899
3 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2,3 = 5v, v extvcc = 0v, v drvset = 0v, vprg3 = float unless otherwise noted. order information electrical characteristics lead free finish tape and reel part marking* package description temperature range ltc3899efe#pbf ltc3899efe#trpbf ltc3899fe 38-lead plastic tssop C40c to 125c ltc3899ife#pbf ltc3899ife#trpbf ltc3899fe 38-lead plastic tssop C40c to 125c ltc3899hfe#pbf ltc3899hfe#trpbf ltc3899fe 38-lead plastic tssop C40c to 150c ltc3899mpfe#pbf ltc3899mpfe#trpbf ltc3899fe 38-lead plastic tssop C55c to 150c ltc3899euhf#pbf ltc3899euhf#trpbf 3899 38-lead (5 mm 7mm) plastic qfn C40c to 125c ltc3899iuhf#pbf ltc3899iuhf#trpbf 3899 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3899huhf#pbf ltc3899huhf#trpbf 3899 38-lead (5mm 7mm) plastic qfn C40c to 150c ltc3899mpuhf#pbf ltc3899mpuhf#trpbf 3899 38-lead (5mm 7mm) plastic qfn C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v bias bias input supply operating voltage range 4.5 60 v v fb1,2 buck regulated feedback voltage (note 4) ith1,2 voltage = 1.2v 0c to 85c l 0.792 0.788 0.800 0.800 0.808 0.812 v v v fb3 boost regulated feedback voltage (note 4) ith3 voltage = 1.2v vprg3 = float vprg3 = 0v vprg3 = intv cc l l l 1.182 9.78 11.74 1.200 10.00 12.00 1.218 10.22 12.26 v v v i fb1,2 buck feedback current (note 4) C2 50 na i fb3 boost feedback current (note 4) vprg3 = float vprg3 = 0v vprg3 = intv cc 0.01 4 5 0.05 6 7 a a a v reflnreg reference voltage line regulation (note 4) v bias = 4.5v to 60v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop, ?ith voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in servo loop, ?ith voltage = 1.2v to 2v l C0.01 C0.1 % g m1,2,3 transconductance amplifier g m (note 4) ith1,2,3 = 1.2v, sink/ source 5a 2 mmho ltc 3899 3899fa for more information www.linear.com/ltc3899
4 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2,3 = 5v, v extvcc = 0v, v drvset = 0v, vprg3 = float unless otherwise noted. symbol parameter conditions min typ max units i q input dc supply current (note 5), v drvset = 0v pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2,3 = 0v or run2 = 5v and run1,3 = 0v or run3 = 5v and run1,2 = 0v, v fb1,2 = 0.83v (no load), v fb3 = 1.25v 1.6 1.6 0.8 ma pulse-skipping or forced continuous mode (all channels on) run1,2,3 = 5v, v fb1,2 = 0.83v (no load), v fb 3 = 1.25v 3 ma sleep mode (one channel on, buck) run1 = 5v and run2,3 = 0v or run2 = 5v and run1,3 = 0v v fb1,2 = 0.83v (no load) l 29 55 a sleep mode (one channel on, boost) run3 = 5v and run1,2 = 0v, v fb3 = 1.25v 29 50 a sleep mode (buck and boost channel on) run1 = 5v and run2 = 0v or run2 = 5v and run1 = 0v, run3 = 5v, v fb1,2 = 0.83v (no load), v fb3 = 1.25v 34 55 a sleep mode (all three channels on) run1,2,3 = 5v, v fb1,2 = 0.83v (no load), v fb3 = 1.25v 39 60 a shutdown run1,2,3 = 0v 3.6 10 a uvlo undervoltage lockout drv cc ramping up drvset = 0v or r drvset 100k drvset = intv cc l l 4.0 7.5 4.2 7.8 v v drv cc ramping down drvset = 0v or r drvset 100k drvset = intv cc l l 3.6 6.4 3.8 6.7 4.0 7.0 v v v ovl1,2 buck feedback overvoltage protection measured at v fb1,2 relative to regulated v fb1,2 7 10 13 % i sense1,2 + sense + pin current bucks (channels 1 and 2) 1 a i sense3 + sense + pin current boost (channel 3) 170 a i sense1,2 C sense C pins current bucks (channels 1 and 2) v out1,2 < v intvcc C 0.5v v out1,2 > v intvcc + 0.5v 700 1 a a i sense3 C sense C pin current boost (channel 3) v sense +, v sense C = 12v 1 a df max(tg) maximum duty factor for tg bucks (channels 1,2) in dropout, freq = 0v boost (channel 3) in overvoltage 97.5 99 100 % % df max(bg) maximum duty factor for bg bucks (channels 1,2) in overvoltage boost (channel 3) 100 96 % % i track/ss1,2 soft-start charge current v track/ss1,2 = 0v 8 10 12 a i ss soft-start charge current v ss3 = 0v 8 10 12 a v run1,2,3 on run pin on threshold v run1 , v run2 , v run3 rising l 1.22 1.275 1.33 v v run1,2,3 hyst run pin hysteresis 75 mv v sense(max) maximum current sense threshold v fb1,2 = 0.7v, v sense1,2 C = 3.3v, v fb3 = 1.1v, v sense3 + = 12v l 65 75 85 mv v sense(cm) sense3 pins common mode range (boost converter input supply voltage) 2.2 60 v gate driver tg1,2,3 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 bg1,2,3 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 ltc 3899 3899fa for more information www.linear.com/ltc3899
5 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2,3 = 5v, v extvcc = 0v, v drvset = 0v, vprg3 = float unless otherwise noted. symbol parameter conditions min typ max units bdsw1,2,3 boost to drv cc switch on-resistance v sw = 0v, v drvset = intv cc 3.7 tg1,2,3 t r tg1,2,3 t f tg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns bg1,2,3 t r bg1,2,3 t f bg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns tg1,2/bg1,2 t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver, v drvset = intv cc 55 ns bg1,2/tg1,2 t 1d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver, v drvset = intv cc 50 ns tg3/bg3 t 1d ch3 top gate off to bottom gate on delay bottom switch-on delay time c load = 3300pf each driver, v drvset = intv cc 85 ns bg3/tg3 t 1d ch3 bottom gate off to top gate on delay synchronous switch-on delay time c load = 3300pf each driver, v drvset = intv cc 80 ns t on(min)1,2 buck minimum on- time (note 7) v drvset = intv cc 80 ns t on(min)3 boost minimum on- time (note 7) v drvset = intv cc 120 ns drv cc linear regulator v drvcc (int) drv cc voltage from internal v bias ldo v extvcc = 0v 7v < v bias < 60v, drvset = 0v 11v < v bias < 60v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v v ldoreg(int) drv cc load regulation from v bias ldo i cc = 0ma to 50ma, v extvcc = 0v 0.9 2.0 % v drvcc (ext) drv cc voltage from internal extv cc ldo 7v < v extvcc < 13v, drvset = 0v 11v < v extvcc < 13v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v v ldoreg(ext) drv cc load regulation from internal extv cc ldo i cc = 0ma to 50ma, v extvcc = 8.5v, v drvset = 0v 0.7 2.0 % v extvcc extv cc ldo switchover voltage extv cc ramping positive drvset = 0v or r drvset 100k drvset = intv cc 4.5 7.4 4.7 7.7 4.9 8.0 v v v ldohys extv cc hysteresis 250 mv v drvcc (50k) programmable drv cc r drvset = 50k, v extvcc = 0v 5.0 v v drvcc (70k) programmable drv cc r drvset = 70k, v extvcc = 0v 6.4 7.0 7.6 v v drvcc (90k) programmable drv cc r drvset = 90k, v extvcc = 0v 9.0 v oscillator and phase-locked loop f 25k programmable frequency r freq =25k, pllin/mode = dc voltage 105 khz f 65k programmable frequency r freq = 65k, pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq = 105k, pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v, pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc , pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pllin v ih pllin v il pllin/mode input high level pllin/mode input low level pllin/mode = external clock pllin/mode = external clock l l 2.5 0.5 v v boost3 charge pump i bst3 boost3 charge pump available output current freq = 0v, pllin/mode = intv cc v boost3 = 16.5v, v sw3 = 12v v boost3 = 19v, v sw3 = 12v 75 35 a a ltc 3899 3899fa for more information www.linear.com/ltc3899
6 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime. note 2: the ltc3899 is tested under pulsed load conditions such that t j t a . the ltc3899e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3899i is guaranteed over the C40c to 125c operating junction temperature range, the ltc3899h is guaranteed over the C40c to 150c operating junction temperature range, and the ltc3899mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 34c/w for the qfn package and where ja = 25c/w for the tssop package. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3899 is tested in a feedback loop that servos v ith1,2,3 to a specified voltage and measures the resultant v fb1,2,3 . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc3899e and ltc3899i, 150c for the ltc3899h and ltc3899mp). for the ltc3899i and ltc3899h, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C40c. for the ltc3899mp, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current >40% of i max (see minimum on- time considerations in the applications information section). note 8: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. ltc 3899 3899fa for more information www.linear.com/ltc3899
7 typical performance characteristics load step (buck) burst mode operation load step (buck) pulse-skipping mode load step (buck) forced continuous mode inductor current at light load (buck) soft start-up (buck) buck regulated feedback voltage vs temperature efficiency and power loss vs output current (buck) efficiency vs output current (buck) efficiency vs input voltage (buck) output current (a) 0.0001 efficiency (%) power loss (mw) 100 10 90 70 50 30 80 60 40 20 0 10000 1000 100 10 1 0.1 3899 g01 10 0.01 1 0.001 0.1 figure 12 circuit v in = 10v v out = 5v burst efficiency pulse-skipping efficiency fcm efficiency pulse-skipping loss fcm loss burst loss output current (a) 0.0001 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 3899 g02 10 0.01 1 0.001 0.1 figure 12 circuit v out = 5v burst mode operation v in = 10v v in = 20v v in = 30v input voltage (v) 0 efficiency (%) 98 82 94 90 86 96 92 88 84 80 60 20 40 50 10 30 drvset = intv cc drvset = 0v figure 12 circuit v out = 5v i load = 4a 3899 g03 v in = 12v v out = 5v figure 12 circuit 3899 g04 v out 100mv/div ac coupled i l 2a/div 50s/div v in = 12v v out = 5v figure 12 circuit 3899 g05 v out 100mv/div ac coupled i l 2a/div 50s/div v in = 12v v out = 5v figure 12 circuit 3899 g06 v out 100mv/div ac coupled i l 2a/div 50s/div v in = 12v v out = 5v i load = 1ma figure 12 circuit 3899 g07 forced continuous mode pulse- skipping mode 2s/div burst mode operation 1a/div figure 12 circuit 3899 g08 run1, 2 5v/div v out1 2v/div 2ms/div v out2 2v/div temperature (c) -75 regulated feedback voltage (mv) 808 806 802 804 800 796 798 794 792 -25 25 -50 0 75 100 3899 g09 150 50 125 ltc 3899 3899fa for more information www.linear.com/ltc3899
8 typical performance characteristics load step (boost) forced continuous mode load step (boost) pulse-skipping mode load step (boost) burst mode operation inductor current at light load (boost) soft start-up (boost) boost regulated feedback voltage vs temperature efficiency and power loss vs output current (boost) efficiency vs input voltage (boost) output current (a) 0.0001 efficiency (%) power loss (mw) 100 10 90 70 50 30 80 60 40 20 0 10000 1000 100 10 1 0.1 3899 g10 10 0.01 1 0.001 0.1 burst efficiency pulse-skipping efficiency v in = 5v v out = 10v fcm efficiency pulse-skipping loss fcm loss burst loss input voltage (v) 2 efficiency (%) 100 82 98 94 90 86 96 92 88 84 80 12 6 10 4 8 drvset = intv cc drvset = 0v figure 12 circuit v out = 10v i load = 2a 3899 g11 temperature (c) -75 run pin voltage (v) 1.4 1.1 1.15 1.05 1.3 1.35 1.25 1.2 1 -25 25 -50 0 75 100 3899 g12 150 50 125 rising falling v in = 5v v out = 10v figure 12 circuit 3899 g13 v out 500mv/div ac coupled il 5a/div 100s/div v in = 5v v out = 10v figure 12 circuit 3899 g14 v out 500mv/div ac coupled il 5a/div 100s/div v in = 5v v out = 10v figure 12 circuit 3899 g15 v out 500mv/div ac coupled il 5a/div 100s/div v in = 7v v out = 10v i load = 1ma figure 12 circuit 3899 g16 forced continuous mode pulse- skipping mode 2s/div burst mode operation 5a/div figure 12 circuit 3899 g17 run3 5v/div gnd 2ms/div v out3 2v/div temperature (c) -75 regulated feedback voltage (v) 1.212 1.209 1.203 1.206 1.2 1.194 1.197 1.191 1.188 -25 25 -50 0 75 100 3899 g18 150 50 125 shutdown (run) threshold vs temperature ltc 3899 3899fa for more information www.linear.com/ltc3899
9 typical performance characteristics sense pins total input current vs v sense voltage buck sense C pin input bias current vs temperature boost sense pin total input current vs temperature maximum current sense threshold vs duty cycle maximum current sense threshold vs i th voltage track/ss pull-up current vs temperature drv cc line regulation drv cc and extv cc vs load current extv cc switchover and drv cc voltages vs temperature input voltage (v) 0 5 drv cc voltage (v) 11 9 7 10 8 6 5 65 25 45 55 15 35 60 20 40 50 10 30 3899 g19 drvset = intv cc drvset = gnd load current (ma) 0 drv cc voltage (v) 6.4 5.6 4.8 6 5.2 4.4 6.2 5.4 4.6 5.8 5 4.2 4 150 75 25 125 50 100 3899 g20 extv cc = 0v extv cc = 8.5v v bias = 12v drvset = gnd extv cc = 5v temperature (c) -75 drv cc voltage (v) 11 10 8 9 7 5 6 4 -25 25 -50 0 75 100 3899 g21 150 50 125 extv cc rising extv cc falling extv cc rising extv cc falling drv cc drv cc drvset = gnd drvset = intv cc v sense common mode voltage (v) 0 5 sense current (a) 800 500 200 700 400 600 300 100 0 65 25 45 55 15 35 60 20 40 50 10 30 3899 g22 sense1, 2 pins (buck) sense3 pins (boost) temperature (c) -75 sense current (a) 900 800 600 700 500 200 400 100 300 0 -25 25 -50 0 75 100 3899 g23 150 50 125 v out > intv cc + 0.5v v out < intv cc ? 0.5v temperature (c) -75 sense current (a) 200 180 140 160 120 60 100 40 20 80 0 -25 25 -50 0 75 100 3899 g24 150 50 125 v in = 12v sense3 ? pin sense3 + pin duty cycle (%) 0 maximum current sense voltage (a) 100 90 70 80 60 30 50 20 10 40 0 20 40 10 30 60 70 3899 g25 100 50 9080 buck boost v ith (v) 0 maximum current sense voltage (mv) 100 80 60 20 0 ?20 40 ?40 0.4 0.8 0.2 0.6 1.2 3899 g26 1.4 1 5% duty cycle pulse-skipping burst mode operation forced continuous mode temperature (c) -75 track/ss current (a) 12 11.5 11 9.5 10.5 9 8.5 10 8 -25 25 -50 0 75 100 3899 g27 150 50 125 ltc 3899 3899fa for more information www.linear.com/ltc3899
10 typical performance characteristics buck foldback current oscillator frequency vs temperature undervoltage lockout threshold vs temperature boost3 charge pump charging current vs frequency boost3 charge pump charging current vs switch voltage shutdown current vs temperature shutdown current vs input voltage temperature (c) -75 shutdown current (a) 8 7 6 3 5 2 1 4 0 -25 25 -50 0 75 100 3899 g28 150 50 125 v bias = 12v input voltage (v) 0 shutdown current (a) 14 12 6 10 4 2 8 0 20 40 10 30 60 3899 g29 65 50 5 25 45 15 35 55 feedback voltage (mv) 0 maximum current sense voltage (mv) 100 90 70 80 60 30 50 20 10 40 0 200 400 100 300 600 700 3899 g31 800 500 temperature (c) -75 frequency (khz) 600 500 550 450 350 400 300 -25 25 -50 0 75 100 3899 g32 150 50 125 freq = intv cc freq = gnd temperature (c) -75 drv cc voltage (v) 8 5 5.5 4.5 3.5 4 7 7.5 6.5 6 3 -25 25 -50 0 75 100 3899 g33 150 50 125 rising rising falling falling drvset = intv cc drvset = gnd sw3 voltage (v) 5 boost3 ? sw3 voltage (v) 10 2 8 6 4 9 7 5 3 0 1 65 25 45 55 15 35 60 20 40 50 10 30 150c 25c ?55c freq = 350khz 10m load between boost3 and sw3 3899 g34 operating frequency (khz) 100 charge pump charging current (a) 100 90 70 80 60 30 50 20 10 40 0 200 400300 600 700 3899 g35 800 500 v boost3 = 16.5v v sw3 = 12v ? 55c 150c 25c sw3 voltage (v) 0 5 charge pump charging current (a) 120 90 100 110 80 50 20 70 40 60 30 10 0 65 25 45 55 15 35 60 20 40 50 10 30 3899 g36 v boost3 ? v sw3 = 4.5v ? 55c ?55c 150c 25c 150c v boost3 ? v sw3 = 7.0v 25c freq = 350khz boost3 charge pump output voltage vs sw3 voltage ltc 3899 3899fa for more information www.linear.com/ltc3899 75 100 125 150 0 10 20 30 40 50 60 70 80 quiescent current (a) quiescent current vs temperature 3899 g30 v bias = 12v one channel on burst mode operation drvset = 70k drvset = intv cc temperature (c) drvset = gnd ?75 ?50 ?25 0 25 50
11 pin functions (qfn/tssop) freq (pin 1/ pin 5): the frequency control pin for the internal vco. connecting this pin to gnd forces the vco to a fixed low frequency of 350khz. connecting this pin to intv cc forces the vco to a fixed high frequency of 535 khz . other frequencies between 50 khz and 900 khz can be programmed using a resistor between freq and gnd. the resistor and an internal 20a source current create a voltage used by the internal oscillator to set the frequency. pllin/mode (pin 2/pin 6): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg1 signal to be synchronized with the rising edge of the external clock, and the regulators will operate in forced continuous mode. when not synchronizing to an external clock, this input, which acts on all three controllers, determines how the ltc3899 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated . tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.1v and less than intv cc C 1.3 v selects pulse-skipping operation. this can be done by connecting a 100k resistor from this pin to intv cc . intv cc (pin 8/pin 12): output of the internal 5v low dropout regulator. the low voltage analog and digital circuits are powered from this voltage source . a low esr 0.1f ceramic bypass capacitor should be connected between intv cc and gnd, as close as possible to the ic. intv cc should not be used to power or bias any external circuitry other than to configure freq, pllin/mode, drvset and vprg3 pins. run1, run2, run3 (pins 9, 10, 11/ pins 13, 14, 15): run control inputs for each controller. forcing any of these pins below 1.2v shuts down that controller. forcing all of these pins below 0.7v shuts down the entire ltc3899, reducing quiescent current to approximately 3.6a. drvset (pin 16/pin 20): sets the regulated output volt- age of the drv cc ldo regulator. connecting this pin to gnd sets drv cc to 6v whereas connecting it to intv cc sets drv cc to 10v. voltages between 5v and 10v can be programmed by placing a resistor (50k to 100k) between the drvset pin and gnd . the drvset pin also determines the higher or lower drv cc uvlo and extv cc switchover thresholds, as listed on the electrical characteristics table. connecting drvset to gnd or programming drvset with a resistor chooses the lower thresholds whereas tying drvset to intv cc chooses the higher thresholds. when programming drvset with a resistor, do not choose a resistor value less than 50k (unless shorting drvset to gnd) or higher than 100k. drv cc (pin 22/pin 26): output of the internal or external low dropout (ldo) regulator. the gate drivers are pow- ered from this voltage source . the drv cc voltage is set by the drvset pin. must be decoupled to ground with a minimum of 4.7f ceramic or other low esr capacitor. do not use the drv cc pin for any other purpose. extv cc (pin 23/pin 27): external power input to an inter - nal ldo connected to drv cc . this ldo supplies drv cc power, bypassing the internal ldo powered from v bias whenever extv cc is higher than its switchover threshold (4.7v or 7.7v depending on the drvset pin). see extv cc connection in the applications information section . do not float or exceed 14v on this pin. do not connect extv cc to a voltage greater than v bias . connect to gnd if not used. v bias ( pin 24/ pin 28): main supply pin . a bypass capacitor should be tied between this pin and the gnd pin. bg1, bg2, bg 3 (pins 29, 21, 25/pins 33, 25, 29): high current gate drives for bottom n-channel mosfets . voltage swing at these pins is from ground to drv cc . boost1, boost2, boost 3 (pins 30, 20, 26/pins 34, 24, 30): bootstrapped supplies to the topside floating drivers . capacitors are connected between the boost and sw pins. voltage swing at boost1 and boost2 pins is from approximately drv cc to (v in1,2 + drv cc ). voltage swing at boost3 is from drv cc to (v out3 + drv cc ). sw1, sw2, sw3 (pins 31, 19, 28/pins 35, 23, 32): switch node connections to inductors. tg1, tg2, tg3 (pins 32, 18, 27/ pins 36, 22, 31): high current gate drives for top n - channel mosfets . these are the outputs of floating drivers with a voltage swing equal to drv cc superimposed on the switch node voltage sw. ltc 3899 3899fa for more information www.linear.com/ltc3899
12 pin functions (qfn/tssop) track/ss1, track/ss2, ss 3 (pins 33, 17, 3/pins 37, 21, 7): external tracking and soft-start input. for the buck channels, the ltc3899 regulates the v fb1,2 voltage to the smaller of 0.8v, or the voltage on the track/ss1,2 pin. for the boost channel, the ltc3899 regulates the v fb3 voltage to the smaller of 1.2v, or the voltage on the ss3 pin. an internal 10a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. alternatively, a re- sistor divider on another voltage supply connected to the track/ss pins of the buck channels allow the ltc3899 buck outputs to track the other supply during start-up. vprg3 (pin 34/pin 38): channel 3 output control pin. this pin sets the boost channel to adjustable output mode using external feedback resistors or fixed 10v/12v output mode . floating this pin allows the output to be programmed through the v fb3 pin using external resistors, regulating v fb3 to the 1.2v reference. connecting this pin to gnd or intv cc programs the output to 10v or 12v (respectively), and v fb3 is used to sense the output voltage. ith1, ith2, ith3 (pins 35, 15, 7/ pins 1, 19, 11): error amplifier outputs and switching regulator compensation points. each associated channels current comparator trip point increases with this control voltage. v fb 1 , v fb 2 ( pins 36, 14/ pins 2, 18): these pins receive the remotely sensed feedback voltage for each buck controller from an external resistive divider across the output. v fb3 ( pins 6/pins 10): if vprg3 is floating, this pin receives the remotely sensed feedback voltage for the boost con- troller from an external resistive divider across the output. if vprg3 is tied to gnd or intv cc , this pin receives the remotely sensed output voltage of the boost controller. sense1 + , sense2 + , sense3 + ( pins 37, 13, 4/pins 3, 17, 8): the (+) input to the differential current compara- tors. the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. for the boost channel, the sense3 + pin supplies current to the current comparator. sense1 C , sense2 C , sense3 C ( pins 38, 12, 5/pins 4, 16, 9): the (C) input to the differential current compara- tors. when sense1,2 C for the buck channels is greater than intv cc , then sense1,2 C pin supplies current to the current comparator. gnd (exposed pad pin 39/exposed pad pin 39): ground. the exposed pad must be soldered to the pcb for rated electrical and thermal performance. ltc 3899 3899fa for more information www.linear.com/ltc3899
13 functional diagrams boost1,2 drv cc tg1,2 top bot buck channels 1 and 2 s clk1 clk2 pfd sync det vco q r q bot shdn sleep 0.425v top on sw1,2 bg1,2 drv cc gnd sense1,2 + sense1,2 ? ith1,2 track/ss1,2 shdn run1,2 shdn rst 2(v fb ) foldback 10a v fb1,2 r a r c r b c c 0.80v track/ss 0.88v ov c b c out v in1,2 v out1,2 r sense l switching logic dropout det + ? + ? + ? ? + + i r 3mv i cmp 2.8v 0.65v slope comp + ? + ? c in + ? c c2 c ss 3899 fd 150na 3.5v 20a freq pllin/mode 100k ea intv cc ldo drv cc ldo/ uvlo control 4.7v/ 7.7v en + ? en 2.00v 1.20v drvset extv cc v bias drv cc 20a 4r r + ? + ? intv cc ltc 3899 3899fa for more information www.linear.com/ltc3899
14 functional diagrams boost3 drv cc tg3 top bottom clk1 pllin/mode boost channel 3 s q r q bot shdn sleep 0.425v sw3 bg3 drv cc gnd sense3 ? sense3 + vprg3 ith3 ss3 shdn 10a v fb3 r a r c r b c c 1.2v ss3 1.32v run3 ov ea c b c in v out3 v in3 r sense l switching logic charge pump + ? + ? + ? ? + + i r 3mv i cmp 2.8v 0.7v slope comp + ? + ? c out + ? 2v snslo + ? c c2 c ss 3899 fd02 150na 3.5v snslo v out3 main control loop the ltc3899 uses a constant frequency, current mode step- down architecture . the two buck controllers , channels 1 and 2, operate 180 out of phase with each other. the boost controller, channel 3, operates in phase with chan- nel 1. during normal operation, the external top mosfet for the buck channels (the external bottom mosfet for the boost controller) is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, i cmp , resets the rs latch. the operation (refer to the functional diagrams) peak inductor current at which i cmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output voltage feedback signal at the v fb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage (1.2v reference voltage for the boost). when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current matches the new load current. ltc 3899 3899fa for more information www.linear.com/ltc3899
15 operation (refer to the functional diagrams) releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller. each run pin may be externally pulled up or driven directly by logic . each run pin can tolerate up to 65v (absolute maximum), so it can be conveniently tied to v bias in always-on applications where one or more controllers are enabled continuously and never shut down. the start-up of each controllers output voltage v out is controlled by the voltage on the track / ss pin (track/ss1 for channel 1, track/ss2 for channel 2, ss3 for channel 3). when the voltage on the track/ss pin is less than the 0.8v internal reference for the bucks and the 1.2v internal reference for the boost, the ltc3899 regulates the v fb voltage to the track/ss pin voltage instead of the corresponding reference voltage. this al- lows the track/ss pin to be used to program a soft-start by connecting an external capacitor from the track/ss pin to gnd. an internal 10a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v/1.2v (and beyond up to about 4v), the output voltage v out rises smoothly from zero (v in for the boost) to its final value. alternatively the track/ss pins for buck channels 1 and ?2 can be used to cause the start-up of v out to track that of another supply. typically , this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see applications information section). light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the ltc3899 can be enabled to enter high efficiency burst mode operation , constant frequency pulse - skipping mode , or forced continuous conduction mode at low load currents . to select burst mode operation, tie the pllin/mode pin to gnd. to select forced continuous operation, tie the pllin/ mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.1v and less than intv cc C 1.3v. this can be done by connecting a 100k resistor between pllin/mode and intv cc . when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to ap- proximately 25% of the maximum sense voltage (30% after the top mosfet for the bucks ( the bottom mosfet for the boost) is turned off each cycle, the bottom mosfet is turned on ( the top mosfet for the boost) until either the inductor current starts to reverse , as indicated by the current comparator i r , or the beginning of the next clock cycle. drv cc / extv cc / intv cc power power for the top and bottom mosfet drivers is derived from the drv cc pin. the drv cc supply voltage can be programmed from 5v to 10v through control of the drvset pin. when the extv cc pin is tied to a voltage below its switchover voltage (4.7v or 7.7v depending on the drvset voltage), the v bias ldo (low dropout linear regulator) supplies power from v bias to drv cc . if extv cc is taken above its switchover voltage, the v bias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies power from extv cc to drv cc . using the extv cc pin allows the drv cc power to be derived from a high efficiency external source such as one of the ltc3899 buck regulator outputs. each top mosfet driver is biased from the floating boot- strap capacitor, c b , which normally recharges during each cycle through an internal switch whenever sw goes low. for buck channels 1 and 2, if the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one -twelfth of the clock period every tenth cycle to allow c b to recharge, resulting in about 99% duty cycle. the intv cc supply powers most of the other internal circuits in the ltc3899. the intv cc ldo regulates to a fixed value of 5v and its power is derived from the drv cc supply. shutdown and start-up (run, track/ss pins) the three channels of the ltc3899 can be independently shut down using the run1, run2 and run3 pins. pull- ing a run pin below 1.20v shuts down the main control loop for that channel. pulling all three pins below 0.7v disables all controllers and most internal circuits , including the drv cc and intv cc ldos. in this state, the ltc3899 draws only 3.6a of quiescent current. ltc 3899 3899fa for more information www.linear.com/ltc3899
16 operation (refer to the functional diagrams) for the boost) even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith volt- age drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3899 draws. if one channel is in sleep mode and the other two are shut down, the ltc3899 draws only 29a of quiescent current (with drvset = 0v). if two channels are in sleep mode and the other shut down, it draws only 34a of quiescent current. if all three controllers are enabled in sleep mode, the ltc3899 draws only 39a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet (the bottom external mosfet for the boost) on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i r ) turns off the bottom external mosfet ( the top external mosfet for the boost) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates discontinuously. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry . in forced continuous mode, the output ripple is independent of load current. clocking the ltc3899 from an external source enables forced continuous mode (see the frequency selection and phase-locked loop section). when the pllin/ mode pin is connected for pulse- skipping mode, the ltc3899 operates in pwm pulse- skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet (bottom for the boost) to stay off for the same number of cycles (i.e ., skipping pulses ). the inductor current is not allowed to reverse ( dis - continuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3899s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source , the freq pin can be tied to gnd, tied to intv cc or programmed through an external resistor . tying freq to gnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and gnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 10. a phase-locked loop (pll) is available on the ltc3899 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3899s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn- on of controller 1s external top mosfet (and controller 3s external bottom mosfet) to the rising edge of the synchronizing signal. thus, the turn-on of controller 2s external top mosfet is 180 out of phase to the rising edge of the external clock source. ltc 3899 3899fa for more information www.linear.com/ltc3899
17 operation (refer to the functional diagrams) the vco input voltage is prebiased to the operating fre- quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg1. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the ltc3899s phase-locked loop is from approximately 55khz to 1mhz, with a guaran- tee to be between 75khz and 850khz. in other words, the ltc3899s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.1v (falling). it is recommended that the external clock source swings from ground (0v) to at least 2.5v. boost controller operation when v in > v out when the input voltage to the boost channel rises above its regulated v out voltage, the controller can behave dif- ferently depending on the mode, inductor current and v in voltage. in forced continuous mode, the loop works to keep the top mosfet on continuously once v in rises above v out . an internal charge pump delivers current to the boost capacitor from the boost3 pin to maintain a sufficiently high tg voltage. because the ltc3899 uses internal switches and does not require external bootstrap diodes, the charge pump only has to overcome small leakage currents (board leakage, etc.). in pulse-skipping mode, if v in is between 0% and 10% above the regulated v out voltage, tg3 turns on if the inductor current rises above approximately 3% of the programmed i lim current. if the part is programmed in burst mode operation under this same v in window, then tg3 turns on at the same threshold current as long as the chip is awake ( one of the buck channels is awake and switching). if both buck channels are asleep or shut down in this v in window, then tg3 will remain off regardless of the inductor current. if v in rises more than 10% above the regulated v out voltage in any mode, the controller turns on tg3 regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the entire chip is asleep ( if the two buck channels are also asleep or shut down ). with the charge pump off, there would be nothing to pre- vent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. the charge pump turns back on when the chip wakes up, and it remains on as long as one of the buck channels is actively switching. boost controller at low sense pin common voltage the current comparator of the boost controller is powered directly from the sense3 + pin and can operate to voltages as low as 2.2v. since this is lower than the v bias uvlo of the chip, v bias can be connected to the output of the boost controller, as illustrated in the typical application circuit in figure ?12 . this allows the boost controller to handle input voltage transients down to 2.2v while maintaining output voltage regulation . if sense 3 + falls below 2.0 v , then switching stops and ss3 is pulled low . if sense 3 + rises back above 2.2v, the ss3 pin will be released, initiating a new soft-start sequence. buck controller output overvoltage protection the two buck channels have an overvoltage comparator that guards against transient overshoots as well as other more serious conditions that may overvoltage the output. when the v fb1,2 pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. buck foldback current when the buck output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short - circuit condition . foldback current limiting is disabled during the soft-start interval ( as long as the v fb1,2 voltage is keeping up with the track/ss1,2 voltage). there is no foldback current limiting for the boost channel. ltc 3899 3899fa for more information www.linear.com/ltc3899
18 applications information 3899 f03 to sense filter next to the controller inductor or r sense current flow figure?1. sense lines placement with inductor or sense resistor the typical application on the first page is a basic ltc 3899 application circuit . ltc3899 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. buck controllers ( sense 1 + / sense 1 C , sense 2 + / sense 2 C ): the common mode voltage range on these pins is 0 v to 65v (absolute maximum), enabling the ltc3899 to regu- late buck output voltages up to a nominal 60 v ( allowing margin for tolerances and transients ). the sense + pin is high impedance over the full common mode range, drawing at most 1a . this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage . when sense C is less than intv cc C 0.5 v, a small current of less than 1a flows out of the pin. when sense C is above intv cc + 0.5 v, a higher current (700 a ) flows into the pin . between intv cc C 0.5v and intv cc + 0.5v, the current transitions from the smaller current to the higher current. boost controller ( sense 3 + / sense 3 C ): the common mode input range for these pins is 2.2v to 60v, allowing the boost converter to operate from inputs over this full range. the sense3 + pin also provides power to the cur - rent comparator and draws about 170a during normal operation (when not shut down or asleep in burst mode operation). there is a small bias current of less than 1a that flows into the sense3 C pin. this high impedance on the sense3 C pin allows the current comparator to be used in inductor dcr sensing. filter components mutual to the sense lines should be placed close to the ltc3899, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure?1 ). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable . if dcr sensing is used (figure 2b), r1 should be placed close to the switch- ing node, to prevent noise from coupling into sensitive small-signal nodes. low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparators have a maximum threshold v sense(max) of 75mv. the current comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 when using the buck controllers in very low dropout con- ditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criteria for buck regulators operating at greater than 50% ltc 3899 3899fa for more information www.linear.com/ltc3899
19 3899 f04b ltc3899 boost tg sw bg sense1,2 + (sense3 ? ) sense1,2 ? (sense3 + ) gnd v in1,2 (v out3 ) v out1,2 (v in3 ) c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor . inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3899 is capable of sensing the voltage drop across the inductor dcr, as shown in figure?2 b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r 2/(r 1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section , the target sense resistor value is : r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load cur - rent over the full operating temperature range, determine r sense(equiv) , keeping in mind that the minimum value for the maximum current sense threshold (v sense(max) ) for the ltc3899 is 65mv. next, determine the dcr of the inductor. when provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) applications information 3899 f04a ltc3899 boost tg sw bg sense1,2 + (sense3 ? ) sense1,2 ? (sense3 + ) gnd v in1,2 (v out3 ) v out1,2 (v in3 ) r sense cap placed near sense pins (2 b) using the inductor dcr to sense current (2a) using a resistor to sense current figure?2. current sensing methods ltc 3899 3899fa for more information www.linear.com/ltc3899
20 c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. the equivalent resistance r1||r2 is scaled to the tempera- ture inductance and maximum dcr: ? r1 ? r2 = l (dcr at 20 c)?c1 the sense resistor values are: ? r1 = r1 ? r2 r d ; r2 = r1?r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 for the boost controller, the maximum power loss in r1 will occur in continuous mode at v in = 1/2 ? v out : p loss r1 = v out(max) ? v in ( ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however , dcr sensing eliminates a sense resistor , reduces conduction losses and provides higher efficiency at heavy loads . peak efficiency is about the same with either method . inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered . the inductor value has a direct effect on ripple current. the inductor ripple current, ?i l , decreases with higher inductance or higher frequency. for the buck controllers, ?i l increases with higher v in : ? i l = 1 f ( ) l ( ) v out 1 ? v out v in ? ? ? ? ? ? ? ? ? ? for the boost controller, ?i l increases with higher v out : ? i l = 1 f ( ) l ( ) v in 1 ? v in v out ? ? ? ? ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3( i max ). the maximum ?i l occurs at the maximum input voltage for the bucks and v in = 1/2 ? v out for the boost. the inductor value also has secondary effects. the tran- sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit (30% for the boost) determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. applications information ltc 3899 3899fa for more information www.linear.com/ltc3899
21 applications information ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection tw o external power mosfets must be selected for each controller in the ltc3899: one n-channel mosfet for the top switch (main switch for the bucks , synchronous for the boost), and one n-channel mosfet for the bottom switch (main switch for the boost, synchronous for the bucks). the peak-to-peak drive levels are set by the drv cc volt- age. this voltage can range from 5v to 10v depending on configuration of the drvset pin . therefore , both logic - level and standard-level threshold mosfets can be used in most applications depending on the programmed drv cc voltage. pay close attention to the bv dss specification for the mosfets as well. the ltc3899s unique ability to adjust the gate drive level between 5v to 10v ( opti-drive) allows an application circuit to be precisely optimized for efficiency. when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has im- proved. if there is no change in input current, then there is no change in efficiency. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: buck main switch duty cycle = v out v in buck sync switch duty cycle = v in ? v out v in boost main switch duty cycle = v out ? v in v out boost sync switch duty cycle = v in v out the mosfet power dissipations at maximum output current are given by: p main_buck = v out v in i out(max) ( ) 2 1 + ( ) r ds(on) + (v in ) 2 i out(max) 2 ? ? ? ? ? ? ? ? ? ? (r dr )(c miller )? 1 v drvcc ? v thmin + 1 v thmin ? ? ? ? ? ? ? ? ? ? (f) p sync _buck = v in ? v out v in i out(max) ( ) 2 1 + ( ) r ds(on) p main_boost = v out ? v in ( ) v out v in 2 i out(max) ( ) 2 ? 1 + ( ) r ds(on) + v out 3 v in ? ? ? ? ? ? ? ? ? ? i out(max) 2 ? ? ? ? ? ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v drvcc ? v thmin + 1 v thmin ? ? ? ? ? ? ? ? ? ? (f) p sync _boost = v in v out i out(max) ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. ltc 3899 3899fa for more information www.linear.com/ltc3899
22 applications information both mosfets have i 2 r losses while the main n-channel equations for the buck and boost controllers include an additional term for transition losses, which are highest at high input voltages for the bucks and low input voltages for the boost. for v in < 20 v (higher v in for the boost) the high current efficiency generally improves with larger mosfets , while for v in > 20 v (lower v in for the boost) the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actu- ally provides higher efficiency. the synchronous mosfet losses for the buck controllers are greatest at high input voltage when the top switch duty factor is low or during a short- circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but = 0.005/c can be used as an approximation for low voltage mosfets. optional schottky diodes placed across the synchronous mosfet conduct during the dead-time between the con- duction of the two power mosfets . this prevents the body diode of the synchronous mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. boost c in , c out selection the input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. the boost input capacitor c in voltage rating should comfortably exceed the maximum input voltage . although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not . be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter , the output has a discontinuous current , so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choos- ing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: ripple = i out(max) ? v out ? v in(min) ( ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: ?v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum , special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings such as os -con and poscap. buck c in , c out selection the selection of c in for the two buck controllers is simplified by the 2-phase architecture and its impact on the worst- case rms current drawn through the input network (bat- tery /fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula shown in equa- ltc 3899 3899fa for more information www.linear.com/ltc3899
23 applications information tion 1 to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the opt-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ? ? ? ? ? ? 1/2 (1) this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief . note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3899, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3899 2-phase operation can be cal- culated by using equation 1 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/ battery is included in the efficiency testing. the drains of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v bias pin and ground, placed close to the ltc3899, is also suggested. a 10 resistor placed between c in (c1) and the v bias pin provides further isolation. the selection of c out is driven by the effective series resistance (esr). typically , once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ? v out ? i l esr + 1 8 ? f ?c out ? ? ? ? ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and ?i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. setting buck output voltage the ltc3899 output voltages for the buck controllers are set by an external feedback resistor divider carefully placed across the output, as shown in figure?3 . the regulated output voltage is determined by: v out = 0.8v 1 + r b r a ? ? ? ? ? ? ? ? ? ? to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line. 3899 f05 ltc3899 v fb r b c ff r a v out figure?3. setting buck output voltage ltc 3899 3899fa for more information www.linear.com/ltc3899
24 applications information setting boost output voltage (vprg3 pin) through control of the vprg3 pin the boost controller output voltage can be set by an external feedback resis- tor divider or programmed to a fixed 10v or 12v output. floating vprg3 allows the boost output voltage to be set by an external feedback resistor divider placed across the output, as shown in figure 4a. the regulated output voltage is determined by: v out(boost) = 1.2v 1 + r b r a ? ? ? ? ? ? ? ? ? ? tying the vprg3 to intv cc or gnd configures the boost controller in fixed output voltage mode. figure 4b shows how the v fb3 pin is used to sense the output voltage in this mode. tying vprg3 to intv cc programs the boost output to 12v, whereas tying vprg3 to gnd programs the output to 10v. run pins the ltc3899 is enabled using the run1, run2 and run3 pins. the run pins have a rising threshold of 1.275v with 75mv of hysteresis. pulling a run pin below 1.2v shuts down the main control loop for that channel. pulling all three run pins below 0.7v disables the controllers and most internal circuits , including the drv cc and intv cc ldos. in this state, the ltc3899 draws only 3.6a of quiescent current. releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller. because of condensation or other small board leakage pulling the pin down , it is recommended the run pins be externally pulled up or driven directly by logic. each run pin can tolerate up to 65v (absolute maximum), so it can be conveniently tied to v bias in always-on applications where one or more controllers are enabled continuously and never shut down . the run pins can be implemented as a uvlo by con- necting them to the output of an external resistor divider network off v bias , as shown in figure?5. the rising and falling uvlo thresholds are calculated using the run pin thresholds and pull-up current: v uvlo(rising) = 1.275v 1 + r b r a ? ? ? ? ? ? C 150na ?r b v uvlo(falling) = 1.20v 1 + r b r a ? ? ? ? ? ? C 150na ?r b tracking and soft-start (track/ss1, track/ss2, ss3 pins) the start-up of each v out is controlled by the volt- age on the track/ss pin (track/ss1 for channel 1, track/ss2 for channel 2, ss3 for channel 3). when the voltage on the track/ss pin is less than the internal 0.8v reference (1.2v reference for the boost channel), the ltc3899 regulates the v fb pin voltage to the voltage on the track/ss pin instead of the internal reference. the track/ss pin can be used to program an external soft-start function or to allow v out to track another sup- ply during start-up. 3899 f06a ltc3899 v fb3 vprg3 (float) r b c ff r a v out3 (4a) setting boost output using external resistors 3899 f06b ltc3899 (4b) setting boost to fixed 12v/10v output v fb3 vprg3 intv cc /gnd c out v out3 12v/10v figure?4. setting ch3 output voltage 3899 f13 1/3 ltc3899 run r b r a v bias figure?5. using the run pins as a uvlo ltc 3899 3899fa for more information www.linear.com/ltc3899
25 applications information 3899 f07 ltc3899 track/ss gnd c ss figure?6. using the track/ss pin to program soft-start 3889 f08a v x(master) v out(slave) output (v out ) time (7a) coincident tracking 3899 f08b v x(master) v out(slave) output (v out ) time (7b) ratiometric tracking 3899 f09 ltc3899 v fb1,2 track/ss1,2 r b r a v out r trackb r tracka v x soft -start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure?6 . an internal 10a current source charges the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc3899 will regulate its feedback voltage (and hence v out ) according to the voltage on the track/ss pin, al- lowing v out to rise smoothly from 0v (v in for the boost) to its final regulated value. the total soft-start time will be approximately: t ss _buck = c ss ? 0.8v 10a t ss _boost = c ss ? 1.2v 10a alternatively , the track / ss 1 and track / ss 2 pins for the two buck controllers can be used to track two (or more) supplies during start-up, as shown qualita- tively in figures?7 a and 7b. to do this, a resistor divider should be connected from the master supply (v x ) to the track/ss pin of the slave supply (v out ), as shown in figure?8 . during start-up v out will track v x according to the ratio set by the resistor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb drv cc and intv cc regulators ( opti-drive) the ltc3899 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the drv cc pin from either the v bias supply pin or the extv cc pin depending on the connections of the extv cc and drvset pins. a third p-channel ldo supplies power at the intv cc pin from the drv cc pin. drv cc powers the gate drivers whereas intv cc powers much of the ltc 3899 s internal circuitry . the v bias ldo and the extv cc ldo regulate drv cc between 5v to 10v, depending on how the drvset pin is set. each of these ldos can supply a figure?7. tw o different modes of output voltage tracking figure?8. using the track/ss pin for tracking ltc 3899 3899fa for more information www.linear.com/ltc3899
26 applications information peak current of at least 50ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent in- teraction between the channels. the intv cc supply must be bypassed with a 0.1f ceramic capacitor. the drvset pin programs the drv cc supply voltage as well as the drv cc uvlo and extv cc switchover threshold voltages. table 1 summarizes the different drvset pin configurations along with the voltage settings that go with each configuration. tying the drvset pin to intv cc pro- grams drv cc to 10 v and chooses the higher uvlo / extv cc thresholds . tying the drvset pin to gnd programs drv cc to 6v and chooses the lower uvlo/ extv cc thresholds. by placing a 50 k to 100k resistor between drvset and gnd the drv cc voltage can be programmed between 5v to 10v, as shown in figure?9 . with a resistor on drvset , the lower uvlo/ extv cc thresholds are chosen. table 1 drvset pin drv cc voltage drv cc uvlo rising / falling thresholds extv cc switchover threshold 0v 6v 4.0v / 3.8v 4.7v intv cc 10v 7.5v / 6.7v 7.7v resistor to gnd 50k to 100k 5v to 10v 4.0v / 3.8v 4.7v figure?9. relationship between drv cc voltage and resistor value at drvset pin drvset pin resistor (k) 50 4 drv cc voltage (v) 5 7 8 9 11 55 75 85 3899 f10 6 10 70 95 100 60 65 80 90 high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3899 to be exceeded. the drv cc current, which is dominated by the gate charge current, may be supplied by either the v bias ldo or the extv cc ldo. when the voltage on the extv cc pin is less than its switchover threshold (4.7v or 7.7v as determined by the drvset pin described above), the v bias ldo is enabled. power dissipation for the ic in this case is highest and is equal to v bias ? i drvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction tem- perature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, using the ltc3899 in the qfn package, the drv cc current is limited to less than 40ma from a 40v supply when not using the extv cc supply at a 70c ambient temperature: t j = 70c + (40ma)(40v)(34c/w) = 125c to prevent the maximum junction temperature from be- ing exceeded, the v bias supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v bias . when the voltage applied to extv cc rises above its switch over threshold, the v bias ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above the switchover threshold minus the comparator hysteresis. the extv cc ldo attempts to regulate the drv cc voltage to the voltage as programmed by the drvset pin, so while extv cc is less than this voltage, the ldo is in dropout and the drv cc voltage is approximately equal to extv cc . when extv cc is greater than the programmed voltage, up to an absolute maximum of 14v, drv cc is regulated to the programmed voltage. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the ltc3899s switching regulator outputs (4.7v/7.7v v out 14 v) during normal operation and from the v bias ldo when the output is out of regulation (e.g., start-up, short circuit ). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added ltc 3899 3899fa for more information www.linear.com/ltc3899
27 applications information between the extv cc and drv cc pins. in this case, do not apply more than 10v to the extv cc pin and make sure that extv cc v bias . significant efficiency and thermal gains can be realized by powering drv cc from the output, since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (40ma)(8.5v)(34c/w) = 82c however , for 3.3 v and other low voltage outputs , additional circuitry is required to derive drv cc power from the output . the following list summarizes the four possible connec- tions for extv cc : 1. extv cc grounded. this will cause drv cc to be powered from the internal v bias regulator resulting in increased power dissipation in the ltc 3899 at high input voltages . 2. extv cc connected directly to the output of one of the buck regulators. this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc < v bias . 4. extv cc connected to an output-derived boost network off one of the buck regulators. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v/7.7v. topside mosfet driver supply (c b ) external bootstrap capacitors , c b , connected to the boost pins supply the gate drive voltage for the topside mosfet. the ltc3899 features an internal switch between drv cc and the boost pin for each controller. these internal switches eliminate the need for external bootstrap diodes between drv cc and boost. capacitor c b in the functional diagram is charged through this internal switch from drv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate- source of the mosfet. this enhances the top mos- fet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v drvcc (v boost = v out + v drvcc for the boost controller). the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). fault conditions: buck current limit and current foldback the ltc3899 includes current foldback for the buck chan- nels to help limit load current when the output is shorted to ground. if the buck output voltage falls below 70% of its nominal output level, then the maximum sense volt- age is progressively lowered from 100% to 40% of its maximum selected value. under short- circuit conditions with very low duty cycles, the buck channel will begin cycle skipping in order to limit the short- circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on-time, t on(min) , of the ltc 3899 (80ns), the input volt- age and inductor value: ? i l(sc) = t on(min) v in l ? ? ? ? ? ? ? ? the resulting average short- circuit current is: i sc = 40% ?i lim(max) ? 1 2 ? i l(sc) fault conditions: buck overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of one of the buck regulators rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse ltc 3899 3899fa for more information www.linear.com/ltc3899
28 applications information to protect against a shorted top mosfet if the short oc- curs while the controller is operating. a comparator monitors the buck output for overvoltage conditions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists ; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip (such as drv cc short to ground), the overtemperature shutdown circuitry will shut down the ltc3899. when the junction temperature exceeds approximately 175c, the overtemperature circuitry disables the drv cc ldo , causing the drv cc supply to collapse and effectively shutting down the entire ltc3899 chip. once the junction temperature drops back to the approximately 155c , the drv cc ldo turns back on. long-term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc3899 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the turn-on of controller 2s top mosfet is thus 180 out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, clp, holds the voltage at the vco input. note that the ltc3899 can only be synchronized to an external clock whose frequency is within range of the ltc3899s internal vco, which is nominally 55khz to 1 mhz . this is guaranteed to be between 75 khz and 850 khz . typically , the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.1v. the ltc3899 is guaranteed to synchronize to an external clock that swings up to at least 2.5v and down to 0.5v or less. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchronization. although it is not required that the free- running frequency be near the external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to gnd dc voltage 50khz to 900khz any of the above external clock 75khz to 850khz phase locked to external clock ltc 3899 3899fa for more information www.linear.com/ltc3899
29 applications information minimum on- time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3899 is capable of turning on the top mosfet ( bottom mosfet for the boost controller ). it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min)_buck < v out v in (f) t on(min)_boost < v out ? v in v out (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3899 is approximately 80ns for the bucks and 120ns for the boost. however, for the buck channels as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3899 circuits : 1) ic v bias current, 2) drv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v bias current is the dc supply current given in the electrical characteristics table, which excludes mos- fet driver and control currents. v bias current typically results in a small (<0.1%) loss. 2. drv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from drv cc to ground. the resulting dq/dt is a cur - rent out of drv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying drv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of ( duty cycle)/ (efficiency). for example, in a 20v to 5v application, 10ma of drv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis- tor and input and output capacitor esr. in continuous freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3899 f11 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure?10. relationship between oscillator frequency and resistor value at the freq pin ltc 3899 3899fa for more information www.linear.com/ltc3899
30 applications information mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resis- tance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses ), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet(s) (bot- tom mosfet for the boost), and become significant only when operating at high input (output for the boost) voltages ( typically 20 v or greater ). transition losses can be estimated from: transition loss = (1.7) ? v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load(esr) , where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov- ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti - loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc -coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in figure ?12 circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca- pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response . the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de- ltc 3899 3899fa for more information www.linear.com/ltc3899
31 creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed - loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise-time should be controlled so that the load rise-time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. buck design example as a design example for one channel, assume v in = 12v (nominal), v in = 22v (maximum), v out = 3.3v, i max = 5a, v sense( max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30% ripple current as- sumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: ? i l = v out f ( ) l ( ) 1 ? v out v in(nom) ? ? ? ? ? ? ? ? ? ? ? ? a 4.7h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 80ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 3.3v 22v 350khz ( ) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (65mv): r sense 65mv 5.73a 0.01 ? choosing 1% resistors: r a = 25k and r b = 78.7k yields an output voltage of 3.32v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1 + 0.005 ( ) 50 c ? 25 c ( ) ? ? ? ? ? ? 0.035 ? ( ) + 22v ( ) 2 5a 2 2.5 ? ( ) 215pf ( ) ? 1 6v ? 2.3v + 1 2.3v ? ? ? ? ? ? ? ? 350khz ( ) = 308mw a short- circuit to ground will result in a folded back cur - rent of: i sc = 34mv 0.01 ? ? 1 2 80ns 22v ( ) 4.7h ? ? ? ? ? ? ? ? ? ? = 3.21a with a typical value of r ds(on) and = (0.005/ c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = (3.21a) 2 (1.125) (0.022) = 255mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v o(ripple) = r esr (?i l ) = 0.02 (1.45a) = 29mv p-p applications information ltc 3899 3899fa for more information www.linear.com/ltc3899
32 applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. figure ?11 illustrates the current waveforms present in the various branches of the 2-phase synchronous buck regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets mtop1 and mtop2 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c drvcc must return to the combined c out (C) termi- nals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. does the ltc3899 v fb pins resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). r l1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3899 f12 r sense2 v out2 c out2 figure?11. branch current waveforms for bucks ltc 3899 3899fa for more information www.linear.com/ltc3899
33 applications information 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the drv cc and decoupling capacitor connected close to the ic, between the drv cc and the ground pin? this capacitor carries the mosfet drivers current peaks. 6. keep the switching nodes (sw1, sw2, sw3), top gate (tg1, tg2, tg3), and boost nodes (boost1, boost2, boost3) away from sensitive small- signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3899 and occupy minimum pc trace area. 7. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the drv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit . monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypi- cally 25% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both should multiple controllers be turned on at the same time. a particularly difficult region of operation is when one buck channel is nearing its current comparator trip point when the other buck channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry , the regulator will still maintain control of the output voltage. ltc 3899 3899fa for more information www.linear.com/ltc3899
34 typical applications r b2 649k r a2 68.1k c ith2a 68pf c ith2 2200pf c ss2 0.1f v out2 r ith2 15k tg1 ltc3899 c b1 0.1f mtop1 mbot1 r b1 357k r a1 68.1k l1 4.9h v out1 5v 5a c out1a 220f r sns1 9m bg1 gnd drv cc extv cc sense1 + run1 run2 run3 v bias boost1 v fb1 v fb2 ith1 ith2 track/ss1 track/ss2 v fb3 v out3 c ith3a 820pf c ith3 10nf c intvcc 0.1f c ss3 0.1f r ith3 3.6k ith3 ss3 intv cc freq pllin/mode drvset vprg3 sw1 c ith1a 100pf c ith1 1500pf c ss1 0.1f c bias 0.1f c1 1nf c drvcc 4.7f v out1 c out1b 22f tg2 c b2 0.1f mtop2 mbot2 l2 6.5h v out2 8.5v 3a v out3 10v* c out2a 68f r sns2 15m bg2 sense2 + boost2 sw2 c2 1nf c out2b 4.7f c b3 0.1f mtop3 mbot3 3899 ta02 l3 1.2h v in 2.2v to 60v (start-up above 5v) *v out3 is 10v when v in < 10v, follows v in when v in > 10v c in1 33f 2 c in2 2.2f 3 r sns3 3m c3 1nf c out3a 33f c out3b 2.2f 6 r ith1 15k sense1 ? sense2 ? tg3 bg3 sense3 ? boost3 sw3 sense3 + figure?12. high efficiency wide input range dual 5v/8.5v converter mtop1, mbot1: bsz123n08ns3 mtop2, mbot2: bsz123n08ns3 mtop3, mbot3: bsc042ne7ns3 l1: wurth 744314490 l2: wurth 744314650 l3: wurth 744325120 c out1a : sanyo 6tpb220ml c out2a : sanyo 10tpc68m c in1 , c out3a : suncon 63hvp33m efficiency and power loss vs load current ltc 3899 3899fa for more information www.linear.com/ltc3899 10 20 30 40 50 60 70 80 90 100 load current (a) 0.1 1 10 100 1k 10k efficiency (%) power loss (mw) vs load current ef?ciency and power loss 0.0001 3899 ta02b v in = 12v v out = 5v efficiency power loss 0.001 0.01 0.1 1 10 0
35 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa ltc 3899 3899fa for more information www.linear.com/ltc3899
36 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) ltc 3899 3899fa for more information www.linear.com/ltc3899
37 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/15 clarified intv cc pin functions sw1, sw2, sw3 pin callouts corrected block diagram modified 11 11 13, 14 ltc 3899 3899fa for more information www.linear.com/ltc3899
38 ? linear technology corporation 2015 lt 0915 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3899 figure?13. high efficiency triple 24v/3.3v/5v converter with 10v gate drive related parts typical application part number description comments ltc3859al triple output, buck/buck/boost synchronous controller with 28a burst mode i q 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, i q = 28a, buck v out range: 0.8v to 24v, boost v out up to 60v ltc3892/ltc3892-1 60v, low i q , dual 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4.5v v in 60v, 0.8v v out 0.99v in , i q = 29a ltc3769 low i q synchronous step-up dc/dc controller 4.5v (down to 2.5v after start-up) v in 60 v, v out up to 60v, i q ?=?28 a, pll fixed frequency 50khz to 900khz, 4mm 4mm qfn-24, tssop-20e ltc3784 low i q , multiphase, dual channel single output synchronous step-up dc/dc controller 4.5v (down to 2.5v after start-up) v in 60v, v out up to 60v, pll fixed frequency 50khz to 900khz , i q = 28a LTC3890/LTC3890-1 LTC3890-2/ LTC3890- 3 60v, low i q , dual 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3891 60v, low i q , synchronous step-down dc /dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3857/ltc3857-1 ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step- down dc/dc controller with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3864 60v, low i q , high voltage dc/dc controller with 100% duty cycle fixed frequency 50khz to 850khz, 3.5v v in 60v, 0.8v v out v in , i q = 40a, msop-12e, 3mm 4mm dfn-12 lt ? 8705 80v v in and v out synchronous 4-switch buck-boost dc/dc controller v in range: 2.8v (need extv cc > 6.4v) to 80v, v out range: 1.3v to 80v; 4 regulation loops r b2 357k r a2 68.1k c ith2a 100pf c ith2 2.2nf c ss2 0.1f v out2 r ith2 12.7k tg1 ltc3899 c b1 0.1f mtop1 mbot1 r b1 215k r a1 68.1k l1 2.4h v out1 3.3v 8a c out1a 220f r sns1 6m bg1 gnd drv cc extv cc sense1 + run1 run2 run3 v bias boost1 v fb1 v fb2 ith1 ith2 track/ss1 track/ss2 v fb3 v out3 c ith3a 220pf c ith3 4.7nf c intvcc 0.1f c ss3 0.1f r ith3 4.3k ith3 ss3 intv cc freq pllin/mode drvset vprg3 sw1 c ith1a 100pf c ith1 1500pf c ss1 0.1f c bias 0.1f c1 1nf c drvcc 4.7f v out1 c out1b 47f 2 tg2 c b2 0.1f mtop2 mbot2 l2 3.3h v out2 5v 8a v out3 24v 5a c out2a 220f r sns2 6m bg2 sense2 + boost2 sw2 c2 1nf c out2b 47f 2 c b3 0.1f mtop3 mbot3 3899 ta03 l3 3.7h v in 12v to 60v *v out3 is 24v when v in < 24v, follows v in when v in > 24v c in1 33f 2 c in2 2.2f 3 r sns3 6m c3 1nf c out3a 33f c out3b 2.2f 6 r ith1 10k r b3 232k r a3 12.1k sense1 ? sense2 ? tg3 bg3 sense3 ? boost3 sw3 sense3 + mtop1, mtop2: bsc057n08ns3 mbot1, mbot2: bsc036ne7ns3 mtop3, mbot3: bsc042ne7ns3 l1: wrth 744325240 l2: wrth 744325330 l3: wrth 7443551370 c out1a , c out2a : 6tpb220ml c in1 , c out3a : suncon 63hvp33m ltc 3899 3899fa for more information www.linear.com/ltc3899

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